VLSI BASED PROJECTS

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VLSI Based Projects
VLSI Based Projects
  1. LOW-POWER AND AREA-EFFICIENT CARRY SELECT ADDER
  2. DESIGN AND CHARACTERIZATION OF PARALLEL PREFIX ADDERS USING FPGAs
  3. SIMULATION OF IMAGE ENCRYPTION USING AES ALGORITHM
  4. AN AUTONOMOUS VECTOR/SCALAR FLOATING POINT CO-PROCESSOR FOR FPGAs
  5. A FPGA IEEE-754-2008 DECIMAL64 FLOATING-POINT ADDER / SUBTRACTOR
  6. IMPLEMENTATION OF CONVOLUTIONAL ENCODER AND VITERBI DECODER USING VERILOG HDL
  7. DESIGN AND SIMULATION OF UART SERIAL COMMUNICATION MODULE BASED ON VHDL
  8. DESIGN OF THREE-LIFT CONTROLLER BASED ON FPGA
  9. A REVIEW ON POWER OPTIMIZATION OF LINEAR FEED BACK SHIFT REGISTER (LFSR) FOR LOW POWER BIST
  10. THE DESIGN OF AN 8-BIT CISC CPU BASED ON FPGA
  11. OPTIMIZED DESIGN OF UART IP SOFT CORE BASED ON DMA MODE
  12. DESIGN OF SHA-1 ALGORITHM BASED ON FPGA
  13. IMPLEMENTATION OF NON-PIPE LINED AND PIPE LINED DATA ENCRYPTION STANDARD (DES) USING XILINX VIRTEX-6 FPGA TECHNOLOGY
  14. FPGA IMPLEMENTATION OF PIPELINED 2D-DCT AND QUANTIZATION ARCHITECTURE FOR JPEG IMAGE COMPRESSION
  15. A NEW VLSI ARCHITECTURE OF PARALLEL MULTIPLIER–ACCUMULATOR BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM
  16. TEST DATA COMPRESSION USING EFFICIENT BIT MASK AND DICTIONARY SELECTION METHOD
  17. FPGA IMPLEMENTATION OF EFFICIENT FFT ALGORITHM BASED ON COMPLEX SEQUENCE
  18. SIMPLE TRAFFIC LIGHT CONTROLLER: A DIGITAL SYSTEM DESIGN PRODUCT
  19. IMPLEMENTATION OF FIR FILTER ON FPGA USING DAOBC ALGORITHM
  20. FPGA BASED IMPLEMENTATION OF HIGH PERFORMANCE ARCHITECTURAL LOW LEVEL POWER 32 BIT RISC CORE
  21. A FAST VLSI DESIGN OF SMS4 CIPHER BASED ON TWISTED BDD S-BOX ARCHITECTURE
  22. A FPGA IEEE-754 2008 DECIMAL 64 FLOATING POINT MULTIPLIER
  23. DESIGN AND IMPLEMENTATION OF LOSSLESS HIGH SPEED DATA COMPRESSION AND DECOMPRESSION USING VHDL
  24. DESIGN AND IMPLEMENTATION OF ENCRYPTION MODULE IN DES FOR SECURITY USING VERILOG
  25. DESIGN AND IMPLEMENTATION OF  DECRYPTION MODULE IN DES FOR SECURITY USING VERILOG
  26. IMPLEMENTATION OF REAL TIME CANDY MECHANIC USING VHDL
  27. DESIGN AND IMPLEMENTATION OF PATTERN GENERATOR FOR CIRCUIT UNDER TEST USING VERILOG
  28. EFFICIENT DESIGN OF BUTTERFLY ARCHITECTURE FOR RADIX 8  FAST FOURIER TRANSFORM USING VHDL
  29. DESIGN AND IMPLEMENTATION OF  DIGITAL CODE LOCK USING VHDL
  30. IMPLEMENTATION OF FIRST IN FIRST OUT DESIGN  USING VHDL
  31. VLSI DESIGN OF  TRAFFIC LIGHT CONTROLLER USING VHDL
  32. DESIGN AND IMPLEMENTATION OF  ENCRYPTION MODULE FOR AES CORE USING VERILOG
  33. DESIGN AND IMPLEMENTATION OF  DECRYPTION MODULE FOR AES CORE USING VERILOG
  34. DESIGN AND IMPLEMENTATION OF ELEVATOR CONTROLLER USING VHDL
  35. DESIGN AND IMPLEMENTATION OF  LFSR FOR LOW POWER APPLICATIONS USING VERILOG
  36. DESIGN AND IMPLEMENTATION OF  SERIALIZER AND DESERIALIZER  USING VHDL
  37. IMPLEMENTATION OF  FREQUENCY DISTRIBUTOR MODULE USING VHDL
  38. DESIGN AND IMPLEMENTATION OF  VENDING MACHINE CONTROLLER USING VHDL
  39. DESIGN AND IMPLEMENTATION OF  FINITE IMPULSE RESPONSE FILTER USING VHDL
  40. VLSI DESIGN OF 8 BIT MICROPROCESSOR IMPLEMENTATION USING VHDL
  41. DESIGN AND IMPLEMENTATION OF  ARRAY MULTIPLIER IN VERILOG
  42. DESIGN AND IMPLEMENTATION OF  STATE MACHINE CONTROLLER
  43. DESIGN AND IMPLEMENTATION OF  CONTENT ADDRESSABLE MEMORY USING VHDL
  44. DESIGN AND IMPLEMENTATION OF  HOUSE HOLD ALARM SYSTEM USING VHDL
  45. VLSI DESIGN OF  REDUCED INSTRUCTION SET COMPUTER PROCESSOR CORE USING VHDL
  46. VLSI IMPLEMENTATION OF  MEMORY CORE DESIGN USING VHDL
  47. DESIGN AND IMPLEMENTATION OF RANDOM NUMBER GENERATOR USING VERILOG
  48. DESIGN AND IMPLEMENTATION OF USB TRANSMITTER
  49. DESIGN AND IMPLEMENTATION OF BOOTH MULTIPLIER
  50. DESIGN AND IMPLEMENTATION OF WALLACE TREE MULTIPLIER
  51. PERFORMANCE EVALUATION OF HIGH SPEED AND LOW POWER ADDERS
  52. DESIGN OF AN ATM  (AUTOMATED TELLER MACHINE) CONTROLLER
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