VLSI Based Projects
- LOW-POWER AND AREA-EFFICIENT CARRY SELECT ADDER
- DESIGN AND CHARACTERIZATION OF PARALLEL PREFIX ADDERS USING FPGAs
- SIMULATION OF IMAGE ENCRYPTION USING AES ALGORITHM
- AN AUTONOMOUS VECTOR/SCALAR FLOATING POINT CO-PROCESSOR FOR FPGAs
- A FPGA IEEE-754-2008 DECIMAL64 FLOATING-POINT ADDER / SUBTRACTOR
- IMPLEMENTATION OF CONVOLUTIONAL ENCODER AND VITERBI DECODER USING VERILOG HDL
- DESIGN AND SIMULATION OF UART SERIAL COMMUNICATION MODULE BASED ON VHDL
- DESIGN OF THREE-LIFT CONTROLLER BASED ON FPGA
- A REVIEW ON POWER OPTIMIZATION OF LINEAR FEED BACK SHIFT REGISTER (LFSR) FOR LOW POWER BIST
- THE DESIGN OF AN 8-BIT CISC CPU BASED ON FPGA
- OPTIMIZED DESIGN OF UART IP SOFT CORE BASED ON DMA MODE
- DESIGN OF SHA-1 ALGORITHM BASED ON FPGA
- IMPLEMENTATION OF NON-PIPE LINED AND PIPE LINED DATA ENCRYPTION STANDARD (DES) USING XILINX VIRTEX-6 FPGA TECHNOLOGY
- FPGA IMPLEMENTATION OF PIPELINED 2D-DCT AND QUANTIZATION ARCHITECTURE FOR JPEG IMAGE COMPRESSION
- A NEW VLSI ARCHITECTURE OF PARALLEL MULTIPLIER–ACCUMULATOR BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM
- TEST DATA COMPRESSION USING EFFICIENT BIT MASK AND DICTIONARY SELECTION METHOD
- FPGA IMPLEMENTATION OF EFFICIENT FFT ALGORITHM BASED ON COMPLEX SEQUENCE
- SIMPLE TRAFFIC LIGHT CONTROLLER: A DIGITAL SYSTEM DESIGN PRODUCT
- IMPLEMENTATION OF FIR FILTER ON FPGA USING DAOBC ALGORITHM
- FPGA BASED IMPLEMENTATION OF HIGH PERFORMANCE ARCHITECTURAL LOW LEVEL POWER 32 BIT RISC CORE
- A FAST VLSI DESIGN OF SMS4 CIPHER BASED ON TWISTED BDD S-BOX ARCHITECTURE
- A FPGA IEEE-754 2008 DECIMAL 64 FLOATING POINT MULTIPLIER
- DESIGN AND IMPLEMENTATION OF LOSSLESS HIGH SPEED DATA COMPRESSION AND DECOMPRESSION USING VHDL
- DESIGN AND IMPLEMENTATION OF ENCRYPTION MODULE IN DES FOR SECURITY USING VERILOG
- DESIGN AND IMPLEMENTATION OF DECRYPTION MODULE IN DES FOR SECURITY USING VERILOG
- IMPLEMENTATION OF REAL TIME CANDY MECHANIC USING VHDL
- DESIGN AND IMPLEMENTATION OF PATTERN GENERATOR FOR CIRCUIT UNDER TEST USING VERILOG
- EFFICIENT DESIGN OF BUTTERFLY ARCHITECTURE FOR RADIX 8 FAST FOURIER TRANSFORM USING VHDL
- DESIGN AND IMPLEMENTATION OF DIGITAL CODE LOCK USING VHDL
- IMPLEMENTATION OF FIRST IN FIRST OUT DESIGN USING VHDL
- VLSI DESIGN OF TRAFFIC LIGHT CONTROLLER USING VHDL
- DESIGN AND IMPLEMENTATION OF ENCRYPTION MODULE FOR AES CORE USING VERILOG
- DESIGN AND IMPLEMENTATION OF DECRYPTION MODULE FOR AES CORE USING VERILOG
- DESIGN AND IMPLEMENTATION OF ELEVATOR CONTROLLER USING VHDL
- DESIGN AND IMPLEMENTATION OF LFSR FOR LOW POWER APPLICATIONS USING VERILOG
- DESIGN AND IMPLEMENTATION OF SERIALIZER AND DESERIALIZER USING VHDL
- IMPLEMENTATION OF FREQUENCY DISTRIBUTOR MODULE USING VHDL
- DESIGN AND IMPLEMENTATION OF VENDING MACHINE CONTROLLER USING VHDL
- DESIGN AND IMPLEMENTATION OF FINITE IMPULSE RESPONSE FILTER USING VHDL
- VLSI DESIGN OF 8 BIT MICROPROCESSOR IMPLEMENTATION USING VHDL
- DESIGN AND IMPLEMENTATION OF ARRAY MULTIPLIER IN VERILOG
- DESIGN AND IMPLEMENTATION OF STATE MACHINE CONTROLLER
- DESIGN AND IMPLEMENTATION OF CONTENT ADDRESSABLE MEMORY USING VHDL
- DESIGN AND IMPLEMENTATION OF HOUSE HOLD ALARM SYSTEM USING VHDL
- VLSI DESIGN OF REDUCED INSTRUCTION SET COMPUTER PROCESSOR CORE USING VHDL
- VLSI IMPLEMENTATION OF MEMORY CORE DESIGN USING VHDL
- DESIGN AND IMPLEMENTATION OF RANDOM NUMBER GENERATOR USING VERILOG
- DESIGN AND IMPLEMENTATION OF USB TRANSMITTER
- DESIGN AND IMPLEMENTATION OF BOOTH MULTIPLIER
- DESIGN AND IMPLEMENTATION OF WALLACE TREE MULTIPLIER
- PERFORMANCE EVALUATION OF HIGH SPEED AND LOW POWER ADDERS
- DESIGN OF AN ATM (AUTOMATED TELLER MACHINE) CONTROLLER