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TCON: Timer/ counter Control Register
Bit 7 – TF1: Timer1 Overflow Flag
1 = Timer1 overflow occurred (i.e. Timer1 goes to its max and roll over back to zero).
0 = Timer1 overflow not occurred.
It is cleared through software. In Timer1 overflow interrupt service routine, this bit will get cleared automatically while exiting from ISR.
Bit 6 – TR1: Timer1 Run Control Bit
1 = Timer1 start.
0 = Timer1 stop.
It is set and cleared by the software.
Bit 5 – TF0: Timer0 Overflow Flag
1 = Timer0 overflow occurred (i.e. Timer0 goes to its max and roll over back to zero).
0 = Timer0 overflow not occurred.
It is cleared through software. In Timer0 overflow interrupt service routine, this bit will get cleared automatically while exiting from ISR.
Bit 4 – TR0: Timer0 Run Control Bit
1 = Timer0 start.
0 = Timer0 stop.
It is set and cleared by software.
Bit 3- IE1:
External Interrupt 1 edge flag, set by hardware when interrupt on INT1 pin occurred and cleared by hardware when interrupt get processed.
Bit 2- IT1:
This bit selects external interrupt event type on INT1 pin,
1= sets interrupt on falling edge
0= sets interrupt on low level
Bit 1- IE0:
Interrupt0 edge flag, set by hardware when interrupt on INT0 pin occurred and cleared by hardware when an interrupt is processed.
Bit 0 – IT0:
This bit selects external interrupt event type on INT0 pin.
1= sets interrupt on falling edge 0= sets interrupt on low level